LOGICBC sp. z o.o.

LOGICBC sp. z o.o.

Senior ASIC/ FPGA Verification Engineer

Offer parameters
full office work
Rybnik, Silesian (Poland)
Przemysłowa 13

Technologies we use





About the project

Work on projects for the largest players in ASIC/FPGA world.

Your responsibilities

  • verify digital circuits using SystemVerilog language and the most modern ASIC/FPGA verification methodology – UVM (define verification plans, code UVM testbenches, code simulation tests),
  • drive verification activities and guide junior engineers,
  • create project documentation for designs certifications,
  • work on a structured and well planned projects (we use Requirements Driven Development Processes in our projects).

Our requirements

  • Master’s in computer science, electronics or related fields,
  • 6+ years of experience in verification using SystemVerilog and UVM,
  • very good knowledge of English that allows everyday communication and documentation creation,
  • ability to lead verification activities,
  • at least basics knowledge of scripting languages,
  • experience of using modern simulation tools (Modelsim/Questa, Simvision),
  • a valid work permit for Poland/European Union.

This is how we organize our work

This is how we work

in houseat the client's siteyou have influence on the product
Company Image

Development opportunities we offer

  • intracompany training
  • mentoring
  • technical knowledge exchange within the company

What we offer

  • very competitive salary package adequate to competencies,
  • full employment contract or B2B contract,
  • working on challenging projects,

Recruitment stages

  • 1.
    Recruitment interview

LOGICBC sp. z o.o.

logicBC is a company that provides ASIC/FPGA design and verification services in the Aerospace and Automotive industries. At the moment we are looking for engineers to work with us on ASIC verification project for our client.
I apply to:
LOGICBC sp. z o.o.
LOGICBC sp. z o.o.
Rybnik, Przemysłowa 13, Silesian (Poland)

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