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Offer summary
(Summary generated by AI based on the full job description)
The project focuses on building the backbone for chip security and work on cutting-edge cryptography. Technologies include VHDL/Verilog/SystemVerilog, development for FPGA and ASIC, and interfaces like PCIe, Ethernet, AXI. Responsibilities cover RTL development at block and subsystem level, micro-architecture definition, simulations and synthesis, top-level architecture modeling, integration with IP (e.g. RISC-V), preparing inputs for verification environments, tuning countermeasures against side-channel attacks, and participation in certification and technical documentation.
from: 16 September 2026
to: 16 October 2026
22 000 - 31 000 złgross/ mth.contract of employment (full-time)
Salary details
basic salary
Offer parameters
level:mid • senior
working mode:remote • hybrid
location:Łódź, Łódź
Łódź, Łódź
Requirements
Expected technologies
Vite
Our requirements
- Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field
- 5+ years (Mid-level) or 8+ years for Senior-level of hands-on experience in FPGA design and development.
- Proficient in any VHDL/Verilog/SystemVerilog for RTL design.
- Knowledge of ASIC design process.
- Experience with timing analysis, synthesis, and implementation workflows.
- Experience with high-speed interfaces and protocols such as PCIe, Ethernet, AXI.
- Knowledge of system integration, including embedded processors.
- Ability to work independently or strong cooperation skills to work within a cross-functional team.
- Strong problem-solving and analytical thinking skills.
- EU citizenship.
Optional
- Knowledge in the field of cryptography.
- Experience in side-channel attacks and countermeasures.
- Experience with space technologies and requirements.
- EU/NATO security clearance.
Your responsibilities
- Developing and implementing RTL at block and subsystem level for quantum resistant cryptographic algorithms and cryptographic processors.
- Defining micro-architecture, performing simulations, and synthesizing digital design.
- Top-level architecture modeling and integration with 3rd party IP (e.g. RISC-V).
- Tuning up countermeasures against side-channel attacks.
- Preparing input for verification environment for FPGAs and ASICs.
- Participation in certification and technical documentation development.
- Cooperation with ASIC backend team
About the project
Projects aimed at providing backbone for chip security for dual-use markets.
Working on the latest trends in chip security and cryptography.
This is how we organize our work
This is how we work
in house
What we offer
- Full time Senior and Mid positions
- Participation in projects aimed at providing backbone for chip security for dual-use markets.
- Flexible working hours.
- Ability to work remotely (Hybrid/Full).
- Equity options.
- Broad Technical Ownership.
- Innovation and Cutting-Edge Projects.
- Opportunity to attend closed events with military representatives.
Benefits
- remote work opportunities
- flexible working time
RESQUANT sp. z o.o.
Resquant is a rapidly growing deep-tech startup focused on next-generation chip security and quantum-resistant cryptography solutions for dual-use and high-security applications.
We develop advanced hardware security technologies designed to address emerging threats in post-quantum computing environments, working at the intersection of cryptography, semiconductor engineering, and secure system architecture.
We are building a team of highly skilled engineers passionate about cutting-edge FPGA and ASIC development, secure hardware design, and innovative defense-grade technologies.
This is how we work
FPGA Design Engineer
22k–31k zł / mth. (CoE)
I apply to:
RESQUANT sp. z o.o.
Łódź, Łódź
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