(Summary generated by AI based on the full job description)
The project focuses on verification of digital systems with strong HW–SW interaction. Required skills include SystemVerilog, experience in RTL and FPGA, familiarity with DDR, PCIe, AXI protocols and tools like Vivado and VCS. Responsibilities cover full verification cycle: developing environments from scratch, integrating VIP, defining verification sequences, maintaining reference models, executing test plans and establishing verification methodologies and infrastructure.




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