(Summary generated by AI based on the full job description)
The project focuses on functional verification of complex IP blocks and SoCs using SystemVerilog, UVM, and Specman. Responsibilities include developing constrained-random testbenches, functional coverage models, and RTL debugging. Proficiency with VCS, Xcelium, ModelSim/Questa and digital design fundamentals is required. Tasks involve regression and CI/CD pipeline development as well as participation in design reviews and silicon bringup.




By clicking "Aplikuj" you confirm that you've read and accepted our Terms and Conditions.
This is how the employer processes your data
This site is protected by reCAPTCHA and the Google Privacy Policy and Terms of Service apply.
Need more information?