Verification Engineer
Offer summary

(Summary generated by AI based on the full job description)

The project focuses on functional verification of complex IP blocks and SoCs using SystemVerilog, UVM, and Specman. Responsibilities include developing constrained-random testbenches, functional coverage models, and RTL debugging. Proficiency with VCS, Xcelium, ModelSim/Questa and digital design fundamentals is required. Tasks involve regression and CI/CD pipeline development as well as participation in design reviews and silicon bringup.

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Verification Engineer

Company: Integral Solutions

from: 24 June 2026
to: 24 July 2026
salary not specifiedB2B contract (full-time)
Salary details
basic salary
Offer parameters
level:mid
working mode:remote
location:Warszawa, Masovian
Warszawa, Masovian

Requirements

Expected technologies

SystemVerilog
UVM
Specman
VCS
Xcelium
ModelSim
Questa

Our requirements

  • B.Sc. / M.Sc. / Ph.D. in Electrical Engineering, Computer Engineering, or related field.
  • 5+ years of hands-on VLSI verification experience in an industry setting.
  • Strong proficiency in SystemVerilog and UVM methodology (environments, agents, sequences, scoreboards).
  • Strong proficiency in Specman language & methodology
  • Experience with industry simulation tools: VCS, Xcelium, ModelSim/Questa.
  • Solid understanding of digital design fundamentals, RTL coding, and microarchitecture concepts.
  • Familiarity with assertion-based verification (SVA) and coverage-driven verification

Your responsibilities

  • Develop and maintain constrained-random UVM testbenches for RTL blocks and fullchip verification.
  • Write functional coverage models and coverage closure plans to drive verification completeness.
  • Author and execute directed and random test scenarios targeting corner cases and protocol compliance.
  • Debug simulation failures, identify root causes in RTL, and collaborate with designers on fixes.
  • Develop verification plans (VPlans) based on micro-architecture specifications and track sign-off metrics.
  • Contribute to regression infrastructure, CI/CD pipelines, and EDA tool flow scripting.
  • Participate in design reviews, spec reviews, and silicon bringup activities.

About the project

The ideal candidate will be responsible for verifying the functional correctness of complex digital IP blocks and SoCs using industry-standard methodologies and tools. You will work closely with design, architecture, and software teams to deliver high-quality, silicon-proven designs.

This is how we organize our work

This is how we work

at the client's siteyou focus on a single project at a timeyou can change the projectyou focus on product developmentagilescrum

This is how we work on a project

  • Clean Code
  • DevOps
Company

Development opportunities we offer

  • substantive support from technological leaders
  • technical knowledge exchange within the company
  • time for development of your ideas

Benefits

  • sharing the costs of sports activities
  • private medical care
  • remote work opportunities
  • integration events
  • no dress code
  • christmas gifts
  • employee referral program

Recruitment stages

  • 1.
    Rozmowa telefoniczna – wstępna rozmowa z Rekruterem
  • 2.
    Weryfikacja u klienta – ocena dopasowania do wymagań biz.
  • 3.
    Rozmowa techniczna – spotkanie z przedstawicielem firmy

Integral Solutions

Integral Solutions, Informatica Platinum Partner Enterprise, od ponad 20 lat dostarcza nowoczesne rozwiązania IT dla biznesu, oferując usługi m.in. w zakresie integracji danych, Data Engineering (Big Data) oraz Data Governance. Specjalizując się w rekrutacji pracowników z branży IT, nie tylko w obszarze danych, pomaga Klientom powiększać zespoły projektowe o profesjonalistów IT.
Verification Engineer
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Integral Solutions
Warszawa, Masovian
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