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Offer summary
(Summary generated by AI based on the full job description)
The project focuses on physical implementation of quantum-resistant cryptographic processors. The stack includes Innovus, IC Compiler II / Fusion Compiler, PrimeTime/Tempus and physical verification tools Calibre/IC Validator/Pegasus. Responsibilities cover floorplanning, placement, CTS, routing, timing closure and STA signoff, power planning and analysis (IR-drop, EM), low-power implementations (power domains, level shifters, ABB), synthesis-to-layout handoff and tapeout cooperation with the foundry, plus documentation and certification tasks. Salary range 22 000–33 000 PLN.
from: 16 September 2026
to: 16 October 2026
22 000 - 33 000 złgross/ mth.contract of employment (full-time)
Salary details
basic salary
Offer parameters
level:mid • senior
working mode:remote • hybrid
location:Łódź, Łódź
Łódź, Łódź
Requirements
Expected technologies
Linux
Docker
Jira
Confluence
Optional technologies
AWS
Kubernetes
Our requirements
- Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 5+ years (Mid-level) or 8+ years (Senior-level) of hands-on experience in ASIC back-end / physical design.
- Experience with place-and-route tools (e.g. Innovus, IC Compiler II / Fusion Compiler).
- Strong static timing analysis skills and signoff experience (e.g. PrimeTime, Tempus).
- Experience with physical verification tools (e.g. Calibre, IC Validator, Pegasus) for DRC/LVS.
- Proficiency in floorplanning, clock tree synthesis, power planning, and routing.
- Knowledge of low-power implementation and power intent (UPF/CPF).
- Understanding of the full ASIC design flow and front-end / back-end interaction.
- Familiarity with high-speed interfaces and protocols such as PCIe, Ethernet, and AXI.
- Ability to work independently or strong cooperation skills to work within a cross-functional team.
- Strong problem-solving and analytical thinking skills.
- EU citizenship.
- Candidates must be eligible for employment under a Polish employment contract (UoP).
Optional
- Hands-on experience with the GlobalFoundries 22FDX / FD-SOI process technology.
- Experience with Adaptive Body Bias (ABB) techniques.
- Proven track record in low-power optimization.
- Experience with True Random Number Generators (TRNG) or Physically Unclonable Functions (PUF).
- Experience with side-channel attacks and countermeasures.
- EU/NATO security clearance.
Your responsibilities
- Driving the full physical implementation flow - floorplanning, placement, clock tree synthesis (CTS), and routing — for quantum-resistant cryptographic processors.
- Performing timing closure and static timing analysis (STA) signoff across multiple corners and modes (setup/hold).
- Power planning and analysis, including IR-drop and electromigration (EM) checks.
- Implementing low-power architectures: power domains, level shifters, isolation cells, and the body-bias distribution network required for Adaptive Body Bias (ABB) on GF 22FDX FD-SOI.
- Handling synthesis-to-layout handoff, ECOs, and tapeout preparation in cooperation with the foundry (GlobalFoundries).
- Participation in certification and technical documentation development.
This is how we organize our work
This is how we work
in house
What we offer
- Full-time Senior and Mid-level positions
- Salary range: 22,000–33,000 PLN gross/month, depending on experience and seniority.
- Employment under an employment contract
- Participation in projects aimed at providing a backbone for chip security for dual-use markets.
- Flexible working hours.
- Ability to work remotely (Hybrid/Full).
- Equity options.
- Broad technical ownership.
- Innovation and cutting-edge projects.
- Opportunity to attend closed events with military representatives.
Benefits
- remote work opportunities
- flexible working time
- no dress code
- sharing the commuting costs
RESQUANT sp. z o.o.
Resquant is a rapidly growing deep-tech startup focused on next-generation chip security and quantum-resistant cryptography solutions for dual-use and high-security applications.
We develop advanced hardware security technologies designed to address emerging threats in post-quantum computing environments, working at the intersection of cryptography, semiconductor engineering, and secure system architecture.
We are building a team of highly skilled engineers passionate about cutting-edge FPGA and ASIC development, secure hardware design, and innovative defense-grade technologies.
This is how we work
ASIC Back-End / Physical Design Engineer (multiple)
22k–33k zł / mth. (CoE)
I apply to:
RESQUANT sp. z o.o.
Łódź, Łódź
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